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Why everybody likes using: xor eax,eax?


alaphate

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To slightly clarify.

xor r32, r32

Is preferred because it only takes 2 bytes and 1 clock cycle.

Whereas:

mov r32, imm

Takes 5 bytes and 2 clock cycle's + i(1, 2)...

Overall it's an optimization thing ;) .

KOrUPt.

Edited by KOrUPt
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Yea, something similar is the following one.

Let's say you want to move 1 to EAX. The immediate instruction is this:

B8 01000000			  MOV EAX,1

However, many compilers use this instead:

6A 01					PUSH 1
58 POP EAX

As you see clearly, the last one uses only three bytes... just optimizing code. :)

Cheers

Nacho_dj

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isnt

push 1
pop eax

pretty dumb if you can do

xor eax, eax
inc eax

same bytes, no memory access.

ive seen it before too but always wondered what's the point (besides perhaps increasing readability)

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yeah I always use xor eax,eax inc eax..

In WL API jumps it leaves rome for a ret 04 or 0c. And you can fit it all into the same space as a jmp xxxxxxxx.

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(besides perhaps increasing readability)

As you surely know, this is not always the reason, since there are times you find a more complicated asm code than the sources themselves... Think that compilation is a mechanical process that sometimes 'mix' instructions loosing the logical order, providing you a strange code...

But yes, I agree, yours is still better solution, "imagination is power" :thumbsup:

Cheers

Nacho_dj

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  • 1 month later...

Another trick is to subtract a register from itself therefore always having 0 as the result; just like 'xor eax, eax', it is two bytes;

00401000		   2BC0		   SUB EAX,EAX
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Another trick is to subtract a register from itself therefore always having 0 as the result; just like 'xor eax, eax', it is two bytes;
00401000		   2BC0		   SUB EAX,EAX

What about if the value stored at EAX is a negative?

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  • 2 weeks later...

Take note of the flags, people. These instructions are used in app code, and if checks are made (not necessarily on EAX) later on, flags are fuxxed (with using XOR for instance) ;-)

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first read intel documentation,since pentium zeroing operation before usage doesnt cause stall. and agi is adress generation not pipeline stall.

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first read intel documentation,since pentium zeroing operation before usage doesnt cause stall. and agi is adress generation not pipeline stall.

Ye i tend to say agi when i mean stall

nevertheless, it's 2 cycles or not?

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its shouldnt be 2 cycles only 1, but i always use pentium u v pipelines optimizations. still as i can see now with core 2 duo aligment is more important, using mov ax,[] or non pairable movzx eax,[]

gives result that movzx is faster due we change aligment of later code.

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